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Integrated Circuit Systems, Inc.
ICS9248-199
Frequency Generator for SIS 735/740 with AMD K7 Processor
Recommended Application: Main system clock for SIS 735/740 with AMD K7 chipset. Output Features: * 1 - CPU @ 2.5V * 1 - Differential pair open drain CPU clock * 1 - IOAPIC @ 2.5V * 1 - SDRAM @ 3.3V * 6- PCI @3.3V * 2 - AGP @ 3.3V * 1- 48MHz, @3.3V fixed * 1- 24/48MHz, @3.3V selectable by I2C (Default is 24MHz) * 2- REF @3.3V, 14.318MHz Features: * Programmable output frequency. * Programmable output divider ratios. * Programmable output rise/fall time. * Programmable output skew. * Programmable spread percentage for EMI control. * Watchdog timer technology to reset system if system malfunctions. * Programmable watch dog safe frequency. * Support I2C Index read/write and block read/write operations. * Uses external 14.318MHz crystal. Skew Specifications: * CPU - CPU: < 175ps * PCI - PCI: < 500ps * CPU - SDRAM: < 250ps * AGP - AGP: <175ps * CPU - AGP, PCI: 1-4ns
Frequency Table
Bit 2 FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 7 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 6 Bit 5 Bit 4 CPU FS2 FS1 FS0 0 0 0 66.66 0 0 1 100.00 0 1 0 166.66 0 1 1 133.33 1 0 0 66.66 1 0 1 100.00 1 1 0 100.00 1 1 1 133.33 0 0 0 112.00 0 0 1 124.00 0 1 0 138.00 0 1 1 150.00 1 0 0 100.00 1 0 1 133.33 1 1 0 150.00 1 1 1 160.00 0 0 0 90.00 0 0 1 100.90 0 1 0 103.00 0 1 1 133.90 1 0 0 137.33 1 0 1 137.33 1 1 0 100.90 1 1 1 133.90 0 0 0 107.00 0 0 1 107.00 0 1 0 142.66 0 1 1 110.00 1 0 0 110.00 1 0 1 146.66 1 1 0 166.70 1 1 1 200.00 SDRAM 66.66 100.00 166.66 133.33 100.00 66.66 133.33 100.00 112.00 124.00 138.00 150.00 166.66 166.66 100.00 120.00 90.00 100.90 103.00 133.90 103.00 137.33 133.90 100.90 107.00 142.66 142.66 110.00 146.66 146.66 125.00 200.00 PCI 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.60 31.00 34.50 30.00 31.25 33.33 30.00 30.00 30.00 33.63 34.33 33.48 34.33 34.33 33.48 33.48 35.66 35.66 35.66 36.66 36.66 36.66 31.25 33.33 AGP SEL = 0 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 67.20 62.00 69.00 60.00 62.50 66.66 60.00 60.00 60.00 67.27 68.67 68.67 66.95 68.67 66.95 66.95 71.33 71.33 71.33 73.33 73.33 73.33 66.68 66.66 AGP SEL = 1 50.00 50.00 55.60 50.00 50.00 50.00 50.00 50.00 56.00 46.50 46.00 50.00 50.00 55.30 50.00 48.00 45.00 50.45 51.50 51.56 51.45 50.21 50.21 50.21 53.50 53.50 53.50 55.00 55.00 55.00 55.57 50.00
Pin Configuration
*FS1/REF1 GND GND X1 X2 GND 2 FS2/PCICLK_F 2 FS3/PCICLK0 VDDPCI 2 **FS4/PCICLK1 **PCICLK2 GND **PCICLK3 **PCICLK4 VDDAGP AGPCLK0 AGPCLK1 GND VDD48 48MHz 2 1 AGPSEL/ 24_48MHz GND
2 *FS0/REF0 2
VDDREF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VDDLAPIC IOAPIC* GND VDDL CPUCLKT0 CPUCLKC0 GND VDDL CPUCLK GND NC NC VDDSDR SDRAM GND 2 PCI_STOP# 2 CPU_STOP# 1 PD# 2 SDRAM_STOP# 2 AGP_STOP# SDATA SCLK GND VDD
48-Pin 300mil SSOP
* These are double strength. ** (1X/2X) have single or double strength to drive 2 loads. 1. Internal pull-up, of 120K to VDD. 2. These inputs have a 120K pull down to GND.
Note: Please see full table on page 4.
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ICS9248-199
ICS9248-199
Pin Configuration
PIN NUMBER 1, 11, 17, 21, 25, 36 2 3 4, 5, 8, 14, 20, 24, 26, 34, 39, 42, 46 6 7 9 10 12 16, 15, 13 19, 18 22 23 27 28 29 30 PIN NAME VDD FS0 REF0 FS1 REF1 GND X1 X2 FS2 PCICLK_F FS3 PCICLK0 FS4 PCICLK1 PCICLK (4:2) AGPCLK (1:0) 48MHz AGPSEL 24_48MHz SCLK SDATA AGP_STOP# SDRAM_STOP# TYPE PWR IN OUT IN OUT PWR IN OUT IN OUT IN OUT IN OUT OUT OUT OUT IN OUT IN I/O IN IN DESCRIPTION 3.3V Power supply for SDRAM output buffers, PCI output buffers, reference output buffers and 48MHz output. Frequency select pin. 14.318 MHz reference clock. Frequency select pin. 14.318 MHz reference clock. Ground pin for outputs. Crystal input,nominally 14.318MHz. Crystal output, nominally 14.318MHz. Frequency select pin. PCI clock output, not affected by PCI_STOP#. Frequency select pin. PCI clock output. Frequency select pin. PCI clock output. PCI clock outputs. AGP outputs defined as 2X PCI. These may not be stopped. 48MHz output clock. AGP frequency select pin. Clock output for super I/O/USB default is 24MHz. Clock pin of I2C circuitry 5V tolerant. Data pin for I2C circuitry 5V tolerant. Stops all AGP clocks besides the AGP_F clocks at logic 0 level, when input low. Stops all SDRAM clocks at logic 0 level, when input low (when MODE active). Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. Stops all CPUCLKs clocks at logic 0 level, when input low. Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. SDRAM clock output. No connect pins. CPU clock output. Supply for CPU and IOAPIC clocks at 2.5V nominal. Complementary clocks of differential pair CPU outputs. This clock is 180 out of phase with SDRAM clocks. These open drain outputs need an external 1.5V pull-up. "True" clocks of differential pair CPU outputs. This clock is in phase with SDRAM clocks. This open drain output needs an external 1.5V pull-up. 2.5V clock output.
31 32 33 35 37, 38 40 41, 45, 48 43
PD# CPU_STOP# PCI_STOP# SDRAM NC CPUCLK VDDL CPUCLKC0
IN IN IN OUT OUT PWR OUT
44 47
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CPUCLKT0 IOAPIC
OUT OUT
2
ICS9248-199
General Description
The ICS9248-199 is a single chip clock solution for desktop designs using the Intel Brookdale chipset with PC133 or DDR memory. It provides all necessary clock signals for such a system. The ICS9248-199 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Block Diagram
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum 48MHz 24_48MHz
2
REF (1:0)
CPU DIVDER
Stop
CPUCLK CPUCLKT0 CPUCLKC0
SDATA SCLK FS (4:0) PD# PCI_STOP# CPU_STOP# SDRAM_STOP# AGP_STOP# AGP_SEL
IOAPIC DIVDER
Stop
IOAPIC SDRAM
Control Logic
SDRAM DIVDER
Stop
PCI DIVDER
Stop
Config. Reg.
AGP DIVDER
5
PCICLK (4:0) PCICLK_F
2
AGPCLK (1:0)
Power Groups
VDDCPU = CPU VDDPCI = PCICLK_F, PCICLK VDDSDR = SDRAM VDD48 = 48MHz, 24MHz, fixed PLL VDDA = Core, PLL, X1, X2 VDDAGP=AGP, REF
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ICS9248-199
Serial Configuration Command Bitmap
Bytes 0-3: Are reserved for external clock buffer. Byte4: Functionality and Frequency Select Register (default = 0)
Bit Bit 2 Bit 7 Bit 6 Bit 5 Bit 4 CPU SDRAM FS4 FS3 FS2 FS1 FS0 0 0 0 0 0 66.66 66.66 0 0 0 0 1 100.00 100.00 0 0 0 1 0 166.66 166.66 0 0 0 1 1 133.33 133.33 0 0 1 0 0 66.66 100.00 0 0 1 0 1 100.00 66.66 0 0 1 1 0 100.00 133.33 0 0 1 1 1 133.33 100.00 0 1 0 0 0 112.00 112.00 0 1 0 0 1 124.00 124.00 0 1 0 1 0 138.00 138.00 0 1 0 1 1 150.00 150.00 0 1 1 0 0 100.00 166.66 0 1 1 0 1 133.33 166.66 0 1 1 1 0 150.00 100.00 Bit 2 Bit 7:4 0 1 1 1 1 160.00 1 2 0 . 0 0 1 0 0 0 0 90.00 90.00 1 0 0 0 1 100.90 100.90 1 0 0 1 0 103.00 103.00 1 0 0 1 1 133.90 133.90 1 0 1 0 0 137.33 103.00 1 0 1 0 1 137.33 137.33 1 0 1 1 0 100.90 133.90 1 0 1 1 1 133.90 100.90 1 1 0 0 0 107.00 107.00 1 1 0 0 1 107.00 142.66 1 1 0 1 0 142.66 142.66 1 1 0 1 1 110.00 110.00 1 1 1 0 0 110.00 146.66 1 1 1 0 1 146.66 146.66 1 1 1 1 0 166.70 125.00 1 1 1 1 1 200.00 200.00 0 - Frequency s se ected by h dw Bit 3 1 - Frequency iis sellected by Bar, 2 are select, Latched it 7:4 0 - Normal Bit 1 1 - Spread Spectrum Enabled 0 Ru ing Bit 0 1- -Tristnne all outputs at Description AGP PCI SEL = 0 33.33 66.66 33.33 66.66 33.33 66.66 33.33 66.66 33.33 66.66 33.33 66.66 33.33 66.66 33.33 66.66 33.60 67.20 31.00 62.00 34.50 69.00 30.00 60.00 31.25 62.50 33.33 66.66 30.00 60.00 30.00 60.00 30.00 60.00 33.63 67.27 34.33 68.67 33.48 68.67 34.33 66.95 34.33 68.67 33.48 66.95 33.48 66.95 35.66 71.33 35.66 71.33 35.66 71.33 36.66 73.33 36.66 73.33 36.66 73.33 31.25 66.68 33.33 66.66 Inputs PWD AGP SEL = 1 50.00 50.00 55.60 50.00 50.00 50.00 50.00 50.00 56.00 46.50 46.00 50.00 50.00 55.30 50.00 48.00 45.00 50.45 51.50 51.56 51.45 50.21 50.21 50.21 53.50 53.50 53.50 55.00 55.00 55.00 55.57 50.00 Spread Precentage 0 to -0.5% Down Spread 0 to -0.5% Down Spread +/- 0.25% Center Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread
00000 Note1
0 1 0
Note1: Default at power-up will be for latched logic inputs to define frequency, as defined by Bit 3. Note: PWD = Power-Up Default I2C is a trademark of Philips Corporation
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ICS9248-199
Byte 5: CPU, Active/Inactive Register (1= enable, 0 = disable)
Byte 6: PCI, Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 23 2,3 47 19 18 23 22
PWD DESCRIPTION 1 24M_48M (1: On, 0: Off) REF_1X2X_Control 0 (0: 1x, 1: 2x) APIC1X2X_Control 1 (0: 1x, 1: 2x) 1 AGPCLK1 (Act/Inactive) 1 AGPCLK0 (Act/Inactive) IOAPIC Select 0 (0:16.67 MHz, 1:33.33 MHz) 24M_48M Select 1 (1: 24 MHz, 0: 48 MHz) 0 Reser ved
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD 19 1 18 1 16 1 15 1 13 1 12 1 10 1 23 X
DESCRIPTION Reser ved Reser ved PCICLK4 (Act/Inactive) PCICLK3 (Act/Inactive) PCICLK2 (Act/Inactive) PCICLK1 (Act/Inactive) PCICLK0 (Act/Inactive) AGPSEL (read back)
Byte 7: Control, Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit Bit Bit Bit 5 4 3 2
PIN# 12 13 10 9 3 2 15 16
PWD 0 0 X X X X X X
Bit 1 Bit 0
DESCRIPTION PCLCLK1_1X2X_Control (1: 2x, 0: 1x) PCLCLK2_1X2X_Control (1: 2x, 0: 1x) FS3 (read back) FS2 (read back) FS1 (read back) FS0 (read back) PCLCLK3_1X2X_Control (1: 2x, 0: 1x) PCLCLK4_1X2X_Control (1: 2x, 0: 1x)
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5
ICS9248-199
Byte 8: Byte Count Read Back Register
Bit Bit 7 Bit 6 Bit 5 Bi t 4 Bit 3 Bi t 2 Bi t 1 Bit 0
Name Byte7 Byte6 Byte5 Byte4 Byte3 Byte2 Byte1 Byte0
PWD Description 0 0 0 Note: Writing to this register will configure 0 byte count and how many bytes will be read back, default is 0FH = 15 bytes. 1 1 1 1
Byte 9: Watchdog Timer Count Register*
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
PWD 0 0 0 1 0 0 0 0
Description The decimal representation of these 8 bits correspond to X * 290ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 16 * 290ms = 4.6 seconds.
Byte 10: Programming Enable bit 8 Watchdog Control Register*
Bit Bit 7 Bit 6 Bit 5 Bi t 4 Bi t 3 Bi t 2 Bit 1 Bit 0
Name Program Enable WD Enable WD Alarm SF4 SF3 SF2 SF1 SF0
PWD 0 0 0 0 1 0 0 0
Description Programming Enable bit 0 = no programming. Frequencies are selected by HW latches or Byte0 1 = enable all I2 C programing. Watchdog Enable bit Watchdog Alarm Status 0 = normal 1= alarm status Watchdog safe frequency bits. Writing to these bits will configure the safe frequency corrsponding to Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register*
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Ndiv 8 Mdiv 6 Mdiv 5 Mdiv 4 Mdiv 3 Mdiv 2 Mdiv 1 Mdiv 0
PWD X X X X X X X X
Description N divider bit 8 The decimal respresentation of Mdiv (6:0) corresposd to the reference divider value. Default at power up is equal to the latched inputs selection.
* These bytes are not available in ICS9248A/B/CF-199. Programmable features on these bytes are only for ICS9248D/EF-199.
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ICS9248-199
Byte 12: VCO Frequency N Divider (VCO divider) Control Register*
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Ndiv 7 Ndiv 6 Ndiv 5 Ndiv 4 Ndiv 3 Ndiv 2 Ndiv 1 Ndiv 0
PWD X X X X X X X X
Description The decimal representation of Ndiv (8:0) correspond to the VCO divider value. Default at power up is equal to the latched inputs selecton. Notice Ndiv 8 is located in Byte 11.
Byte 13: Spread Spectrum Control Register*
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name SS 7 SS 6 SS 5 SS 4 SS 3 SS 2 SS 1 SS 0
PWD X X X X X X X X
Description The Spread Spectrum (12:0) bit will program the spread precentage. Spread precent needs to be calculated based on the VCO frequency, spreading profile, spreading amount and spread frequency. It is recommended to use ICS software for spread programming. Default power on is latched FS divider.
Byte 14: Spread Spectrum Control Register*
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Reserved Reserved Reserved SS 12 SS 11 SS 10 SS 9 SS 8
PWD X X X X X X X X
Description Reserved Reserved Reserved Spread Spectrum Bit 12 Spread Spectrum Bit 11 Spread Spectrum Bit 10 Spread Spectrum Bit 9 Spread Spectrum Bit 8
Byte 15: Output Divider Control Register*
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name SD Div 3 SD Div 2 SD Div 1 SD Div 0 CPU Div 3 CPU Div 2 CPU Div 1 CPU Div 0
PWD X X X X X X X X
Description SDRAM clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider. CPU clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider.
* These bytes are not available in ICS9248A/B/CF-199. Programmable features on these bytes are only for ICS9248D/EF-199.
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ICS9248-199
Byte 16: Output Divider Control Register*
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name PCI Div 3 PCI Div 2 PCI Div 1 PCI Div 0 AGP 50MHz Div 3 AGP 50MHz Div 2 AGP 50MHz Div 1 AGP 50MHz Div 0
PWD X X X X X X X X
Description PCI clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 2. Default at power up is latched FS divider. AGP clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider.
Byte 17: Output Divider Control Register*
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Table 1
Name Reser ved Reser ved SD_INV CPU_INV AGP 66MHz Div 3 AGP 66MHz Div 2 AGP 66MHz Div 1 AGP 66MHz Div 0
PWD X X X X X X X X
Description Reser ved Reser ved SDRAM Phase Inversion bit CPUCLK Phase Inversion bit AGP clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to table 1. Default at power up is latched FS divider.
Table 2
Div (3:2) Div (1:0) 00 01 10 11
00 /2 /3 /5 /7
01 /4 /6 /10 /14
10 /8 /12 /20 /28
11 /16 /24 /40 /56
Div (3:2) Div (1:0) 00 01 10 11
00 /4 /3 /5 /7
01 /8 /6 /10 /14
10 /16 /12 /20 /28
11 /32 /24 /40 /56
* These bytes are not available in ICS9248A/B/CF-199. Programmable features on these bytes are only for ICS9248D/EF-199.
0376E--12/23/02
8
ICS9248-199
Byte 18: Group Skew Control Register*
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name CPU_Skew 1 CPU_Skew 0 SD_Skew 1 SD_Skew 0 PCI_Skew 3 PCI_Skew 2 PCI_Skew 1 PCI_Skew 0
PWD 1 0 0 0 0 0 1 0
Description These 2 bits delay the CPUclocks with respect to all other clocks. 00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps These 2 bits delay the SDRAM_OUT with respect to CPUCLK 00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps These 4 bits can change the CPUCLK to PCICLK skew from 1.4ns - 2.9ns. Each binary increment or decrement of PCI_SKEW (3:0) will increase or decrease the delay of the PCI (F,0:1) clocks by 100ps.
Byte 19: Group Skew Control Register*
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name AGP_Skew 3 AGP_Skew 2 AGP_Skew 1 AGP_Skew 0 PCI_Skew 3 PCI_Skew 2 PCI_Skew 1 PCI_Skew 0
PWD Description These 4 bits can change the CPUCLK to 0 AGP skew from 1.4ns - 2.9ns. Default at 0 power up is - 2.5ns. Each binary increment or decrement of AGP_SKEW (3:0) will increase 1 or decrease the delay of the AGP clocks by 0 100ps. These 4 bits can change the CPUCLK to PCI 0 skew from 1.4ns - 2.9ns. Each binary 0 increment or decrement of PCI_SKEW (3:0) 1 will increase or decrease the delay of the PCI 0 (2:4) clocks by 100ps.
Byte 20: Group Skew Control Register*
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name APIC_Skew 3 APIC_Skew 2 APIC_Skew 1 APIC_Skew 0 REF0 REF1 IOAPIC 48MHz
PWD Description These 4 bits can change the CPUCLK to 0 APIC skew from 1.4ns - 2.9ns. Default at 0 power up is - 2.5ns. Each binar y increment or decrement of APIC_SKEW (3:0) will 1 increase or decrease the delay of the CPU 0 clocks by 100ps. 1 REF1 (Act/Inactive) 1 REF0 (Act/Inactive) 1 IOAPIC (Act/Inactive) 1 48MHz (Act/Inactive)
* These bytes are not available in ICS9248A/B/CF-199. Programmable features on these bytes are only for ICS9248D/EF-199.
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ICS9248-199
Byte 21: Slew Rate Control Register*
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name 24/48_Slew 1 24/48_Slew 0 AGP_Slew 1 AGP_Slew 0 APIC_Slew 1 APIC_Slew 0 REF_Slew 1 REF_Slew 0
PWD 0 1 0 1 0 1 0 1
Description 24/48 MHz clock slew rate control bits. 01 = strong; 00, 11 = normal; 10 = weak AGP clock slew rate control bits. 10 = strong; 00, 11 = normal; 01 = weak IOAPIC clock slew rate control bits. 00 = strong; 00, 11 = normal; 10 = weak REF clock slew rate control bits. 10 = strong; 00, 11 = normal; 00 = weak
Byte 22: Slew Rate Control Register*
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Reserved Reserved PCICLK_F 1x2x PCICLK0 Reserved Reserved Reserved Reserved
PWD 0 0 0 0 0 0 0 0
Description Reserved Reserved 0:1x, 1:2x 0:1x, 1:2x Reserved Reserved Reserved Reserved
Byte 23: Slew Rate Control Register*
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name 48MHz Slew 1 CPUCLKT/C Slew 1 CPUCLK Slew 1 SD Slew 1
PWD 0 1 0 1 0 1 0 1
Description 48MHz clock slew rate control bits. 01 = strong; 00, 11 = normal;10 = weak CPUCLKT/C0 clock slew rate control bit. 01 = strong; 00, 11 = normal;10 = weak CPUCLK clock slew rate control bits. 01 = strong; 00, 11 = normal;10 = weak SDRAM clock slew rate control bits. 01 = strong; 00, 11 = normal;10 = weak
Bit 24: Control, Active/Inactive Register* (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 9 44 43 40 PWD 0 0 0 0 0 0 0 1 DESCRIPTION Reserved Reserved Reserved Reserved PCICLK_F (Act/Inactive) CPUCLKT0 (Act/Inactive) CPUCLK_C0 (Act/Inactive) CPUCLK (Act/Inactive)
* These bytes are not available in ICS9248A/B/CF-199. Programmable features on these bytes are only for ICS9248D/EF-199.
0376E--12/23/02
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ICS9248-199
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . 5.5 V GND -0.5 V to VDD +0.5 V 0C to +70C 115C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL IDD CL =30 pF PCI, SDRAM, 20 pF other outputs Operating Supply Current IDDL Power Down PD VDD = 3.3 V Input frequency Fi Input Capacitance Transistion Time 1 Settling Time 1 Clk Stabilization 1 Skew
1
MIN 2 VSS - 0.3
12 27
MAX UNITS VDD + 0.3 V 0.8 V 180 mA 134 39 mA 27 280 600 uA 14.318 16 MHz 5 45 3 11 1.8 1.6 15 4 4 pF pF ms ms ms ns ns
TYP
1
CIN CINX Ttrans Ts TSTAB
TCPU - PCI 1 TCPU - AGP Skew 1 Guaranteed by design, not 100% tested in production.
Logic Inputs X1 & X2 pins To 1st crossing of target frequency From 1st crossing to 1% of target frequency From VDD = 3.3 V to 1% of target frequency VT = 1.5 V; VTL = 50% VDD VT = 1.5 V; VTL = 50% VDD
1 1
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ICS9248-199
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70C; VDD=3.3V +/- 5%; CL = 20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 VO=VX Output Impedance ZO Output High Voltage VOH2B Termination to Vpull-up(external) Termination to Vpull-up(external) Output Low Voltage VOL2B IOL2B VOL = 0.3 V Output Low Current Fall Time
1 1
MIN 1 18
TYP 50
MAX 1.2 0.4
UNITS V V mA ns V V V % ps ps ps
tf2B
1
Differential voltage-AC 1 Differential voltage-DC 1 Diff Crossover Voltage Duty Cycle
1
1
VDIF VDIF VX dt2B
1 1
VOH = 1.1V, VOL = 2.0V VOH = 80% VDD, VOL = 20% VDD Note 2 Note 2 Note 3
1.7 1.1 0.4 0.2 1.2
1.45 53 47 40 105
2 1.2 Vpull-up(ext) + 0.6 Vpull-up(ext) + 0.6 1.6 55 55 175 250 250
Skew CPUCLK to CPUT0
Jitter, Cycle-to-cycle 1 Jitter, Absolute
1
tsk2B 1 tjcyc-cyc2B 1 tjabs2B
CPUT0,C0 between crossing poin 45 44 CPUT0,C0 VT = 50% VDD VT = 50% VT = VX VT = 50% -250
Notes: 1 - Guaranteed by design, not 100% tested in production. 2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true" input level and VCP is the "complement" input level. 3 - Vpull-up(external) = 2.7V, Min=Vpull-up(external)/2-150mV; Max=Vpull-up(external)/2 +150mV
Electrical Characteristics - 24MHz, 48MHz, AGP, REF
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP5B VO=VDD*(0.5) 1 Output Impedance RDSN5B VO=VDD*(0.5) Output High Voltage VOH5 IOH = -14 mA Output Low Voltage VOL5 IOL = 6 mA IOH5 VOH = 2.0 V Output High Current IOL5 VOL = 0.8 V Output Low Current 1 1 Rise Time tr5 VOL = 0.4 V, VOH = 2.4 V 1 1 Fall Time tf5 VOH = 2.4 V, VOL = 0.4 V Duty Cycle
1 1
MIN 20 20 2.4
TYP
MAX 60 60 0.4 -20
10 1.3 1.3 45 45 52 55 100 110 220 375 2 2 55 56 175 500
UNITS V V mA mA ns ns % ps ps
dt5
1
VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
1
24_48 MHz, AGP REF AGP 24_48 MHz AGP REF
Skew AGP to AGP
tsk5
1
1
Jitter, Cycle-to-Cycle
1
tjcyc-cyc5
VT = 1.5 V VT = 1.5 V
500
Guaranteed by design, not 100% tested in production.
0376E--12/23/02
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ICS9248-199
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP1B VO=VDD*(0.5) Output Impedance1 RDSN1B VO=VDD*(0.5) IOH = -18 mA Output High Voltage VOH1 IOL = 9.4 mA Output Low Voltage VOL1 IOH1 VOH = 2.0 V Output High Current IOL1 VOL = 0.8 V Output Low Current 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V Fall Time1 tf1 VOH = 2.4 V, VOL = 0.4 V dt1 VT = 1.5 V Duty Cycle1 Skew Window1 tsk1 VT = 1.5 V Jitter, Cycle-to-Cycle1 tcyc-cyc1 VT = 1.5 V
1
MIN 12 12 2.6
TYP
MAX 55 55 0.4 -22
25 1.7 1.8 51 170 265 2.0 2.0 55 500 500
45
UNITS V V mA mA ns ns % ps ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP3 VO=VDD*(0.5) 1 Output Impedance RDSN3 VO=VDD*(0.5) Output High Voltage VOH3 IOH = -28 mA Output Low Voltage VOL3 IOL = 19 mA IOH3 VOH = 2.0 V Output High Current IOL3 VOL = 0.8 V Output Low Current 1 Rise Time tr3 VOL = 0.4 V, VOH = 2.4 V 1 Fall Time tf3 VOH = 2.4 V, VOL = 0.4 V 1 dt3 VT = 1.5 V Duty Cycle VT = 1.5 V 100, 133 MHz 1 tcyc-cyc3 Jitter, Cycle-to-Cycle 166 MHz 1 Guaranteed by design, not 100% tested in production. MIN 10 10 2.4 TYP MAX 20 20 0.4 -42 33 0.8 0.6 50 150 280 1.5 1.5 55 250 350 UNITS V V mA mA ns ns % ps
45
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ICS9248-199
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP4B VO=VDD*(0.5) 1 Output Impedance RDSN4B VO=VDD*(0.5) IOH = -14 mA Output High Voltage VOH4 IOL = 6 mA Output Low Voltage VOL4 IOH4 VOH = 2.0 V Output High Current IOL4 VOL = 0.8 V Output Low Current 1 Rise Time tr4 VOL = 0.4 V, VOH = 2.4 V 1 Fall Time tf4 VOH = 2.4 V, VOL = 0.4 V 1 dt4 VT = 1.5 V 24_48 MHz, AGP Duty Cycle Jitter, Cycle-to-Cycle
1 1
MIN 20 20 2.4
TYP
MAX 60 60 0.4 -20
10 0.7 0.8 45 50 235 2 2 55 500
UNITS V V mA mA ns ns % ps
tjcyc-cyc4
VT = 1.5 V
24_48 MHz
Guaranteed by design, not 100% tested in production.
0376E--12/23/02
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ICS9248-199
General I2C serial interface information How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P Not acknowledge stoP bit
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ICS9248-199
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248199 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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ICS9248-199
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9248-199. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
INTERNAL CPUCLK PCICLK CPU_STOP# PD# (High)
CPUCLKT CPUCLKC
Notes: 1. All timing is referenced to the internal CPU clock. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9248-199. 3. All other clocks continue to run undisturbed.
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ICS9248-199
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-199. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-199 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-199 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248-199. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state.
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ICS9248-199
SDRAM_STOP# Timing Diagram
SDRAM_STOP# is an asychronous input to the clock synthesizer. It is used to stop SDRAM clocks for low power operation. SDRAM_STOP# is synchronized to complete it's current cycle, by the ICS9248-199. All other clocks will continue to run while the SDRAM clocks are disabled. The SDRAM clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.
Notes: 1. All timing is referenced to the internal CPU clock. 2. SDRAM is an asynchronous input and metastable conditions may exist. This signal is synchronized to the SDRAM clocks inside the ICS9248-199. 3. All other clocks continue to run undisturbed.
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ICS9248-199
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLKT CPUCLKC
PCICLK VCO Crystal
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-199 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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ICS9248-199
N
c
SYMBOL
L
INDEX AREA
E1
E
12 D h x 45
a
A A1
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS9248yF-199-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
0376E--12/23/02
21

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